Front-end EDA software & lab environment

High-performance multi-language simulation engine for modern ASIC and SoC design. Comprehensive support for SystemVerilog, UVM testbenches, assertions (SVA), mixed-signal, and unified coverage metrics.

• SystemVerilog IEEE 1800 & UVM 1.2 Verification
• Assertion-based verification (SVA) & Code Coverage
• Fast debug environment with advanced waveform viewer

Industry-benchmark simulation and debug environment for FPGA and ASIC design flows. Standardized across academic institutions and silicon teams for robust VHDL, Verilog, and SystemVerilog verification.

• Complete VHDL & Verilog IEEE-compliant simulation
• Native graphical debugger, source browser & datapath viewing
• Full compatibility with Intel Quartus & AMD Vivado flows